Inclusively is partnering with a electronic design automation company to hire a Principal SOC Verification Engineer. **Please note: this role is NOT an internal position with Inclusively but with the partner company.**

ABOUT INCLUSIVELY

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What You’ll Be Doing:

• Defining and tracking Verification test plans
• Designing and writing constrained-random SystemVerilog testbenches using UVM
• Writing SystemVerilog assertions
• Writing functional coverage
• Debugging RTL and GLS failures
• Conducting code coverage analysis
• Providing mentoring and guidance to less experienced team members

The Impact You Will Have:

• Ensuring the highest quality and performance of our ASIC designs
• Contributing to the successful delivery of high-performance computing solutions
• Supporting the development of innovative technologies for a wide range of applications
• Enhancing the efficiency and effectiveness of our verification processes
• Strengthening our reputation as a leader in chip design and verification
• Driving continuous improvement and innovation within the team

What You’ll Need:

• BSEE in Electrical Engineering with 10+ years of industry experience
• Proficiency in digital verification in a UVM environment; formal verification experience is a plus
• Knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture
• Hand on experience with verification tools such as VCS, waveform analyzer and VIP integration
• Expertise in Verilog, SystemVerilog, and Perl/Python scripting

Who You Are:

• An excellent communicator with strong problem-solving skills
• A detail-oriented individual with a passion for quality and performance
• A collaborative team player who enjoys mentoring and guiding others
• An innovative thinker who stays current with industry trends and technologies
• A proactive and self-motivated professional with a strong work ethic